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Features
* 2.4-GHz Radio Transceiver * Operates in the Unlicensed Industrial, Scientific, and Medical (ISM) Band * * * * * * * * * * * * *
(2.4 GHz to 2.483 GHz) -95 dBm Reception Sensitivity Up to 0 dBm Output Power Range of up to 50 Meters or More Data Throughput of up to 62.5 kbits/s Highly Integrated, Low Cost, Minimal Number of External Components Required Dual DSSS Reconfigurable Baseband Correlators SPI Microcontroller Interface (up to 2-MHz Data Rate) 13-MHz Input Clock Operation Low Standby Current < 1 A Integrated 32-bit Manufacturing ID Operating Voltage from 2.7 V to 3.6 V Operating Temperature from -40C to +85C Offered in a Small Footprint QFN48 Package
WirelessUSBTM 2.4-GHz DSSS Radio SoC ATR2434
Applications
* PC Human Interface Devices
- Mice - Keyboards - Joysticks * Peripheral Gaming Devices - Game Controllers - Console Keyboards * General - Presenter Tools - Remote Controls - Consumer Electronics - Barcode Scanners - POS Peripherals - Toys
Preliminary
Functional Description
The ATR2434 transceiver is a single-chip 2.4-GHz Direct Sequence Spread Spectrum (DSSS) Gaussian Frequency Shift Keying (GFSK) baseband modem radio that connects directly to a microcontroller.
Rev. 4822C-ISM-09/04
Figure 1. Simplified Block Diagram
D IO V A L D IO SERDES A DSSS B aseband A GFSK M o d u la to r RFOUT
IR Q SS SCK M IS O M OSI
D ig ita l
SERDES B
DSSS B aseband B
GFSK D e m o d u la to r
R F IN
RESET PD
S y n th e s iz e r
Pin Configuration
Figure 2. Pinning QFN48
RFIN VCC VCC VCC VCC NC NC X13 NC NC NC NC
X13IN X13 X13OUT
48 47 46 45 44 43 42 41 40 39 38 NC NC NC NC RFOUT VCC NC NC VCC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
GND VCC DIOVAL DIO NC NC NC RESET
37 36 35 34 33 32 31 NC X13IN PACTL PD VCC NC NC VCC VCC NC X13OUT SCK
ATR2434
30 29 28 27 26 25 21 22 23 24
SS MOSI MISO IRQ
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Pin Description
Pin No. Analog RF 46 5 38 35 26 33 14 34 20 19 21 23 24 25 22 6, 9, 16, 28, 29, 32, 41, 42, 44, 45 13 1, 2, 3, 4, 7, 8, 10, 11, 12, 15, 17, 18, 27, 30, 31, 36, 37, 39, 40, 43, 47, 48 Exposed paddle RFIN RFOUT X13 X13IN X13OUT PD RESET PACTL DIO DIOVAL IRQ MOSI MISO SCK SS Input Output Input Input Output/Hi-Z Input Input I/O I/O I/O Output/Hi-Z Input Output/Hi-Z Input Input Input N/A N/A N/A Output N/A N/A Input Input Input Output N/A Hi-Z N/A N/A RF input. Modulated RF signal received. RF output. Modulated RF signal to be transmitted. Crystal input (see section "Clocking and Power Management" on page 5). Crystal input (see section "Clocking and Power Management" on page 5). System clock. Buffered 13-MHz system clock. Power down. Asserting this input (low), will put the IC in the suspend mode (X13OUT is 0 when PD is low). Active LOW reset. Device reset. PACTL. External power amplifier control. Pull-down or make output. Data input/output. SERDES bypass mode data transmit/receive. Data I/O valid. SERDES bypass mode data transmit/receive valid. IRQ. Interrupt and SERDES bypass mode DIOCLK. Master-output-slave-input data. SPI data input pin. Master-input-slave-output data. SPI data output pin. SPI input clock. SPI clock. Slave select enable. SPI enable. Symbol Type Default Function
Crystal/Power Control
SERDES Bypass Mode Communications/Interrupt
SPI Communications
Power and Ground VCC GND VCC GND H L VCC = 2.7 V to 3.6 V. Ground = 0 V.
NC
N/A
N/A
Tie to ground.
GND
GND
L
Must be tied to ground.
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Applications Support
The ATR2434 is supported by both the WirelessUSB Development Kit and the WirelessUSB N:1 Development Kit. The development kit provides all of the materials and documents needed to cut the cord on multipoint to point and point to point low bandwidth high node density applications including four small form-factor sensor boards and a hub board that connect to WirelessUSB RF module boards, comprehensive WirelessUSB protocol code examples and all of the associated schematics, gerber files and bill of materials. The WirelessUSB N:1 Development Kit is also supported by the WirelessUSB Listener Tool. The ATR2434 provides a complete WirelessUSB SPI to antenna radio modem. The ATR2434 is designed to implement wireless devices operating in the worldwide 2.4-GHz Industrial, Scientific, and Medical (ISM) frequency band (2.400 GHz to 2.4835 GHz). It is intended for systems compliant with world-wide regulations covered by ETSI EN 301 489-1 V1.4.1, ETSI EN 300 328-1 V1.3.1 (European Countries); FCC CFR 47 Part 15 (USA and Industry Canada) and ARIB STD-T66 (Japan). The ATR2434 contains a 2.4-GHz radio transceiver, a GFSK modem and a dual DSSS reconfigurable baseband. The radio and baseband are both code- and frequency-agile. Forty-nine spreading codes selected for optimal performance (Gold codes) are supported across 78 1-MHz channels yielding a theoretical spectral capacity of 3822 channels. The ATR2434 supports a range of up to 50 meters or more.
Functional Overview
2.4-GHz Radio
The receiver and transmitter are a single-conversion low-Intermediate Frequency (low-IF) architecture with fully integrated IF channel matched filters to achieve high performance in the presence of interference. An integrated Power Amplifier (PA) provides an output power control range of 30 dB in seven steps. Both the receiver and transmitter integrated Voltage Controlled Oscillator (VCO) and synthesizer have the agility to cover the complete 2.4-GHz GFSK radio transmitter ISM band. The VCO loop filter is also integrated on-chip.
GFSK Modem
The transmitter uses a DSP-based vector modulator to convert the 1-MHz chips to an accurate GFSK carrier. The receiver uses a fully integrated Frequency Modulator (FM) detector with automatic data slicer to demodulate the GFSK signal.
Dual DSSS Baseband
Data is converted to DSSS chips by a digital spreader. De-spreading is performed by an oversampled correlator. The DSSS baseband cancels spurious noise and assembles properly correlated data bytes. The DSSS baseband has four operating modes: 64 chips/bit single channel, 32 chips/bit dual channel, 32 chips/bit single channel 2 x oversampled, and 32 chips/bit single channel Dual Data Rate (DDR).
64 Chips/Bit Single Channel
The baseband supports a single data stream operating at 15.625 kbits/s. The advantage of selecting this mode is its ability to tolerate a noisy environment. This is because the 15.625 kbits/s data stream utilizes the longest PN code resulting in the highest probability for recovering packets over the air. This mode can also be selected for systems requiring data transmissions over longer ranges.
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ATR2434 [Preliminary]
32 Chips/Bit Dual Channel The baseband supports two non-simultaneous data streams each operating at 31.25 kbits/s. The baseband supports a single data stream operating at 31.25 kbits/s that is sampled twice as much as the other modes. The advantage of selecting this mode is its ability to tolerate a noisy environment. The baseband spreads bits in pairs and supports a single data stream operating at 62.5 kbits/s. The ATR2434 provides a data Serializer/Deserializer (SERDES), which provides byte-level framing of transmit and receive data. Bytes for transmission are loaded into the SERDES and receive bytes are read from the SERDES via the SPI interface. The SERDES provides double buffering of transmit and receive data. While one byte is being transmitted by the radio the next byte can be written to the SERDES data register insuring there are no breaks in transmitted data. After a receive byte has been received it is loaded into the SERDES data register and can be read at any time until the next byte is received, at which time the old contents of the SERDES data register will be overwritten.
32 Chips/Bit Single Channel 2 x Oversampled
32 Chips/Bit Single Channel Dual Data Rate (DDR)
Serializer/Deserializer (SERDES)
Application Interfaces
The ATR2434 has a fully synchronous SPI slave interface for connectivity to the application MCU. Configuration and byte-oriented data transfer can be performed over this interface. An interrupt is provided to trigger real time events. An optional SERDES Bypass mode (DIO) is provided for applications that require a synchronous serial bit-oriented data path. This interface is for data only.
Clocking and Power Management
A 13-MHz crystal is directly connected to X13IN and X13 without the need for external capacitors. The ATR2434 has a programmable trim capability for adjusting the on-chip load capacitance supplied to the crystal. The Radio Frequency (RF) circuitry has onchip decoupling capacitors. The ATR2434 is powered from a 2.7 V to 3.6 V DC supply. The ATR2434 can be shutdown to a fully static state using the PD pin. Below are the requirements for the crystal to be directly connected to X13IN and X13: * * * * * * * Nominal frequency: 13 MHz Operating mode: fundamental mode Resonance mode: parallel resonant Frequency stability: 30 ppm Series resistance: 100 Load capacitance: 10 pF Drive level: 10 W to 100 W
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Receive Signal Strength Indicator (RSSI)
The RSSI register (Reg 0x22) returns the relative signal strength of the ON-channel signal power and can be used to: 1. determine the connection quality, 2. determine the value of the noise floor, and 3. check for a quiet channel before transmitting. The internal RSSI voltage is sampled through a 5-bit Analog-to-Digital Converter (ADC). A state machine controls the conversion process. Under normal conditions, the RSSI state machine initiates a conversion when an ON-channel carrier is detected and remains above the noise floor for over 50 s. The conversion produces a 5-bit value in the RSSI register (Reg 0x22, bits 4:0) along with a valid bit, RSSI register (Reg 0x22, bit 5). The state machine then remains in HALT mode and does not reset for a new conversion until the receive mode is toggled off and on. Once a connection has been established, the RSSI register can be read to determine the relative connection quality of the channel. A RSSI register value lower than 10 indicates that the received signal strength is low, a value greater than 28 indicates a strong signal level. To check for a quiet channel before transmitting, first set up the receive mode properly and read the RSSI register (Reg 0x22). If the valid bit is zero, then force the Carrier Detect register (Reg 0x2F, bit 7 = 1) to initiate an ADC conversion. Then, wait a minimum of 50 s and read the RSSI register again. Next, clear the Carrier Detect register (Reg 0x2F, bit 7 = 0) and turn the receiver OFF. Measuring the noise floor of a quiet channel is inherently a noisy process so, for best results, this procedure should be repeated several times (~20) to compute an average noise floor level. A RSSI register value of 0-10 indicates a channel that is relatively quiet. A RSSI register value greater than 10 indicates the channel is probably being used. A RSSI register value greater than 28 indicates the presence of a strong signal.
Application Interfaces
SPI Interface
The ATR2434 has a four-wire SPI communication interface between an application MCU and one or more slave devices. The SPI interface supports single-byte and multibyte serial transfers. The four-wire SPI communications interface consists of Master Out-Slave In (MOSI), Master In-Slave Out (MISO), Serial Clock (SCK), and Slave Select (SS). The SPI receives SCK from an application MCU on the SCK pin. Data from the application MCU is shifted in on the MOSI pin. Data to the application MCU is shifted out on the MISO pin. The active-low Slave Select (SS) pin must be asserted to initiate an SPI transfer. The application MCU can initiate an SPI data transfer via a multi-byte transaction. The first byte is the Command/Address byte, and the following bytes are the data bytes as shown in Table 1 on page 7 and Figure 3 through Figure 5 on page 7. The SS signal should not be deasserted between bytes. The SPI communications is as follows: * * Command direction (bit 7) = 0 enables SPI read transaction. A 1 enables SPI write transactions. Command increment (bit 6) = 1 enables SPI auto address increment. When set, the address field automatically increments at the end of each data byte in a burst access, otherwise the same address is accessed. Six bits of address. Eight bits of data.
* *
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The SPI communications interface has a burst mechanism, where the command byte can be followed by as many data bytes as desired. A burst transaction is terminated by deasserting the slave select (SS = 1). The SPI communications interface single read and burst read sequences are shown in Figure 3 and Figure 4, respectively. The SPI communications interface single write and burst write sequences are shown in Figure 5 and Figure 6 on page 8, respectively. Table 1. SPI Transaction Format
Byte 1 Bit # Bit Name 7 DIR 6 INC [5:0] Address Byte 1 + N [7:0] Data
Figure 3. SPI Single Read Sequence
SCK SS cm d M OSI M IS O
D IR
addr
A5 A4 A3 A2 A1 A0
0
IN C
0
d a ta to m c u
D7 D6 D5 D4 D3 D2 D1 D0
Figure 4. SPI Burst Read Sequence
SCK SS cm d MOSI M IS O
D IR
addr
A5 A4 A3 A2 A1 A0
0
IN C
1
d a ta to m c u
D7 D6 D5 D4 D3 D2
1
D1 D0 D7
d a ta to m c u
D6 D5 D4 D3 D2
1+N
D1 D0
Figure 5. SPI Single Write Sequence
SCK SS cm d M OS I M ISO
DIR
addr
A5 A4 A3 A2 A1 A0 D7
data from m cu
D6 D5 D4 D3 D2 D1 D0
1
INC
0
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Figure 6. SPI Burst Write Sequence
SCK SS cm d M OSI M IS O
D IR
a d dr
A5 A4 A3 A2 A1 A0 D7
da ta from m cu
D6 D5 D4 D3 D2
1
D1 D0 D7
d a ta fro m m cu
D6 D5 D4 D3 D2
1 +N
D1 D0
1
IN C
1
DIO Interface
The DIO communications interface is an optional SERDES bypass data-only transfer interface. In receive mode, DIO and DIOVAL are valid after the falling edge of IRQ, which clocks the data as shown in Figure 7. In transmit mode, DIO and DIOVAL are sampled on the falling edge of the IRQ, which clocks the data as shown in Figure 8. The application MCU samples the DIO and DIOVAL on the rising edge of IRQ.
Figure 7. DIO Receive Sequence
IRQ DIOVAL DIO
v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v...
data to mcu
d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d...
Figure 8. DIO Transmit Sequence
IRQ DIOVAL DIO
v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v...
data from mcu
d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d...
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ATR2434 [Preliminary]
Interrupts
The ATR2434 features three sets of interrupts: transmit, receive, and a wake interrupt. These interrupts all share a single pin (IRQ), but can be independently enabled/ disabled. In transmit mode, all receive interrupts are automatically disabled, and in transmit mode all receive interrupts are automatically disabled. However, the contents of the enable registers are preserved when switching between transmit and receive modes. Interrupts are enabled and the status reads through 6 registers: Receive Interrupt Enable (Reg 0x07), Receive Interrupt Status (Reg 0x08), Transmit Interrupt Enable (Reg 0x0D), Transmit Interrupt Status (Reg 0x0E), Wake Enable (Reg 0x1C), Wake Status (Reg 0x1D). If more than 1 interrupt is enabled at any time, it is necessary to read the relevant interrupt status register to determine which event caused the IRQ pin to assert. Even when a given interrupt source is disabled, the status of the condition that would otherwise cause an interrupt can be determined by reading the appropriate interrupt status register. It is therefore possible to use the devices without making use of the IRQ pin at all. Firmware can poll the interrupt status register(s) to wait for an event, rather than using the IRQ pin. The polarity of all interrupts can be set by writing to the Configuration register (Reg 0x05), and it is possible to configure the IRQ pin to be open drain (if active low) or open source (if active high). Wake Interrupt When the PD pin is low, the oscillator is stopped. After PD is deasserted, the oscillator takes time to start, and until it has done so, it is not safe to use the SPI interface. The wake interrupt indicates that the oscillator has started, and that the device is ready to receive SPI transfers. The wake interrupt is enabled by setting bit 0 of the Wake Enable register (Reg 0x1C, bit 0 = 1). Whether or not a wake interrupt is pending is indicated by the state of bit 0 of the Wake Status register (Reg 0x1D, bit 0). Reading the Wake Status register (Reg 0x1D) clears the interrupt. Transmit Interrupts Four interrupts are provided to flag the occurrence of transmit events. The interrupts are enabled by writing to the Transmit Interrupt Enable register (Reg 0x0D), and their status may be determined by reading the Transmit Interrupt Status register (Reg 0x0E). If more than 1 interrupt is enabled, it is necessary to read the Transmit Interrupt Status register (Reg 0x0E) to determine which event caused the IRQ pin to assert. The function and operation of these interrupts are described in detail in the section "Register Descriptions" on page 10. Receive Interrupts Eight interrupts are provided to flag the occurrence of receive events, four each for SERDES A and B. In 64 chips/bit and 32 chips/bit DDR modes, only the SERDES A interrupts are available, and the SERDES B interrupts will never trigger, even if enabled. The interrupts are enabled by writing to the Receive Interrupt Enable register (Reg 0x07), and their status may be determined by reading the Receive Interrupt Status register (Reg 0x08). If more than one interrupt is enabled, it is necessary to read the Receive Interrupt Status register (Reg 0x08) to determine which event caused the IRQ pin to assert. The function and operation of these interrupts are described in detail in the section "Register Descriptions" on page 10.
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Register Descriptions
Table 2. Register Map(1)
Register Name Revision ID Synthesizer A Counter Synthesizer N Counter Control Data Rate Configuration SERDES Control Receive Interrupt Enable Receive Interrupt Status Receive Data A Receive Valid A Receive Data B Receive Valid B Transmit Interrupt Enable Transmit Interrupt Status Transmit Data Transmit Valid PN Code Threshold Low Threshold High Wake Enable Wake Status Analog Control Channel Receive Signal Strength Indicator Power Control Crystal Adjust VCO Calibration AGC Control Carrier Detect Clock Manual Clock Enable Synthesizer Lock Count Manufacturing ID Note:
Table 2 displays the list of registers inside the ATR2434 that are addressable through the SPI interface. All registers are read and writable, except where noted.
Mnemonic REG_ID REG_SYN_A_CNT REG_SYN_N_CNT REG_CONTROL REG_DATA_RATE REG_CONFIG REG_SERDES_CTL REG_RX_INT_EN REG_RX_INT_STAT REG_RX_DATA_A REG_RX_VALID_A REG_RX_DATA_B REG_RX_VALID_B REG_TX_INT_EN REG_TX_INT_STAT REG_TX_DATA REG_TX_VALID REG_PN_CODE REG_THRESHOLD_L REG_THRESHOLD_H REG_WAKE_EN REG_WAKE_STAT REG_ANALOG_CTL REG_CHANNEL REG_RSSI REG_PA REG_CRYSTAL_ADJ REG_VCO_CAL REG_AGC_CTL REG_CARRIER_DETECT REG_CLOCK_MANUAL REG_CLOCK_ENABLE REG_SYN_LOCK_CNT REG_MID
Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11-0x18 0x19 0x1A 0x1C 0x1D 0x20 0x21 0x22 0x23 0x24 0x26 0x2E 0x2F 0x32 0x33 0x38 0x3C-0x3F
Default 0x07 0x00 0x00 0x00 0x00 0x01 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x1E8B6A3DE0E9B222 0x08 0x38 0x00 0x01 0x04 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x64 -
Access RO RW RW RW RW RW RW RW RO RO RO RO RO RW RO RW RW RW RW RW RW RO RW RW RO RW RW RW RW RW RW RW RW RO
1. All registers are accessed Little Endian.
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Table 3. Revision ID Register
Addr: 0x00 7 6 Silicon ID 5 4 REG_ID 3 2 Product ID 1 Default: 0x07 0
Bit 7:4 3:0
Name Silicon ID Product ID
Description These are the Silicon ID revision bits. 0000 = Rev A, 0001 = Rev B, etc. These bits are read-only. These are the Product ID revision bits. Fixed at value 0111. These bits are read-only.
Table 4. Synthesizer A Counter
Addr: 0x01 7 6 Reserved 5 REG_SYN_A_CNT 4 3 2 Count 1 Default: 0x00 0
Bit 7:5 4:0
Name Reserved Count
Description These bits are reserved and should be written with zeros. The Synthesizer A Counter register is used for diagnostic purposes and is not recommended for normal operation. The Channel register is the recommended method of setting the Synthesizer frequency. The Synthesizer A Count along with the Synthesizer N Count can be used to generate the Synthesizer frequency. The range of valid values of the Synthesizer A Count is 0 through 31. Using the Synthesizer A and N Count register is an alternative to using the Channel register. Selection between the use of the Channel register or the A and N registers is done through the Channel register (Reg 0x21, bit 7). When in Channel mode the A and N Count bits can be used to read the A and N values derived directly from the Channel.
Table 5. Synthesizer N Counter
Addr: 0x02 7 Reserved 6 5 REG_SYN_N_CNT 4 3 Count 2 1 Default: 0x00 0
Bit 7 6:0
Name Reserved Count
Description This bit is reserved and should be written with zero. The Synthesizer N Counter register is used for diagnostic purposes and therefore is not recommended for normal operation. The Channel register is the recommended method of setting the Synthesizer frequency. The Synthesizer N Count along with the Synthesizer A Count can be used to generate the Synthesizer frequency. The range of valid values of the Synthesizer N Count is 74 through 76. Using the Synthesizer A and N Count register is an alternative to using the Channel register. Selection between the use of the Channel register or the A and N registers is done through the Channel register (Reg 0x21, bit 7). When in Channel mode the A and N Count bits can be used to read the A and N values derived directly from the Channel.
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Table 6. Control
Addr: 0x03 7 RX Enable 6 TX Enable 5 PN Code Select REG_CONTROL 4 Auto Syn Count Select 3 Auto PA Disable 2 PA Enable 1 Auto Syn Disable Default: 0x00 0 Syn Enable
Bit 7
Name RX Enable
Description The Receive Enable bit is used to place the IC in receive mode. 1 = Receive Enabled 0 = Receive Disabled The Transmit Enable bit is used to place the IC in transmit mode. 1 = Transmit Enabled 0 = Transmit Disabled The Pseudo-noise Code Select bit selects between the upper or lower half of the 64 chips/bit PN code. 1 = 32 Most Significant Bits of PN code are used 0 = 32 Least Significant Bits of PN code are used This bit applies only when the Code Width bit is set to 32 chips/bit PN codes (Reg 0x04, bit 2 = 1). The Auto Synthesizer Count Select bit is used to select the method of determining the settle time of the synthesizer. The two options are a programmable settle time based on the value in the Syn Lock Count register (Reg 0x38), in units of 2 s, or by the auto detection of the synthesizer lock. 1 = Synthesizer settle time is based on a count in the Syn Lock Count register (Reg 0x38) 0 = Synthesizer settle time is based on the internal synthesizer lock signal It is recommended that the Auto Syn Count Select bit is set to 1 as that guarantees a consistent settle time for the synthesizer. The Auto Power Amplifier Disable bit is used to determine the method of controlling the Power Amplifier. The two options are automatically controlled by the baseband or by firmware through register writes. 1 = Register controlled PA Enable. 0 = Auto PA Enable When this bit is set to 1 the state of the PA enable is directly controlled by bit PA Enable (Reg 0x03, bit 2). It is recommended that this bit is set to 0 leaving the PA control to the baseband. The PA Enable bit is used to enable or disable the Power Amplifier. 1 = Power Amplifier Enabled 0 = Power Amplifier Disabled This bit only applies when the Auto PA Disable bit is selected (Reg 0x03, bit 3 = 1), otherwise this bit is do not care. The Auto Synthesizer Disable bit is used to determine the method of controlling the Synthesizer. The two options are automatic control by the baseband or by firmware through register writes. 1 = Register controlled Synthesizer Enable 0 = Auto Synthesizer Enable When this bit is set to 1 the state of the Synthesizer is directly controlled by bit Syn Enable (Reg 0x03, bit 0). When this bit is set to 0 the state of the Synthesizer is controlled by the Auto Syn Count Select bit (Reg 0x03, bit 4). It is recommended that this bit be set to 0 leaving the Synthesizer control to the baseband. The Synthesizer Enable bit is used to enable or disable the Synthesizer. 1 = Synthesizer Enabled 0 = Synthesizer Disabled This bit only applies when Auto Syn Disable bit is selected (Reg 0x03, bit 1 = 1), otherwise this bit is do not care.
6
TX Enable
5
PN Code Select
4
Auto Syn Count Select
3
Auto PA Disable
2
PA Enable
1
Auto Syn Disable
0
Syn Enable
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Table 7. Data Rate
Addr: 0x04 7 6 5 Reserved REG_DATA_RATE 4 3 2 Code Width 1 Data Rate Default: 0x00 0 Sample Rate
Bit 7:3 2
(1)
Name Reserved Code Width
Description These bits are reserved and should be written with zeros. The Code Width bit is used to select between 32 chips/bit and 64 chips/bit PN codes. 1 = 32 chips/bit PN codes 0 = 64 chips/bit PN codes The number of chips/bit used impacts a number of factors such as data throughput, range and robustness to interference. By choosing a 32 chips/bit PN-code, the data throughput can be doubled or even quadrupled (when double data rate is set). A 64 chips/bit PN code offers improved range over its 32 chips/bit counterpart as well as more robustness to interference. By selecting to use a 32 chips/bit PN code a number of other register bits are impacted and need to be addressed. These are PN Code Select (Reg 0x03, bit 5), Data Rate (Reg 0x04, bit 1), and Sample Rate (Reg 0x04, bit 0). The Data Rate bit allows the user to select a Double Data Rate mode of operation which delivers a raw data rate of 62.5 kbits/sec. 1 = Double Data Rate - 2 bits per PN code (No odd bit transmissions) 0 = Normal Data Rate - 1 bit per PN code This bit is applicable only when using 32 chips/bit PN codes which can be selected by setting the Code Width bit (Reg 0x04, bit 2 = 1). When using the Double Data Rate, the raw data throughput is 62.5 kbits/s because every 32 chips/bit PN code is interpreted as 2 bits of data. When using this mode a single 64 chips/bit PN code is placed in the PN code register. This 64 chips/bit PN code is then split into two and used by the baseband to offer the Double Data Rate capability. When using the Normal Data Rate, the raw data throughput is 32 kbits/sec. Additionally, Normal Data Rate enables the user to potentially correlate data using two differing 32 chips/bit PN codes. The Sample Rate bit allows the use of the 12 xsampling when using 32 chips/bit PN codes and the Normal Data Rate. 1 = 12 x Oversampling 0 = 6 x Oversampling Using 12 x oversampling improves the correlators receive sensitivity. When using 64 chips/bit PN codes or the Double Data Rate this bit is do not care. When in the Normal Data Rate setting and choosing 12 x oversampling, eliminates the ability to receive from two different PN codes. Therefore the only time when 12 x oversampling is to be selected is when a 32 chips/bit PN code is being used and there is no need to receive data from sources with two different PN codes.
1(1)
Data Rate
0(1)
Sample Rate
Note:
1. The following Reg 0x04, bits 2:0 values are not valid: * 001-Not Valid * 010-Not Valid * 011-Not Valid * 111-Not Valid
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Table 8. Configuration
Addr: 0x05 7 6 Reserved 5 4 Receive Invert REG_CONFIG 3 Transmit Invert 2 Reserved 1 IRQ Pin Select Default: 0x01 0
Bit 7:5 4
Name Reserved Receive Invert Transmit Invert Reserved IRQ Pin Select
Description These bits are reserved and should be written with zeros. The Receive Invert bit is used to invert the received data. 1 = Inverted over-the-air Receive data 0 = Non-inverted over-the-air Receive data The Transmit Invert bit is used to invert the data that is to be transmitted. 1 = Inverted Transmit Data 0 = Non-inverted Transmit Data This bit is reserved and should be written with zero. The Interrupt Request Pin Select bits are used to determine the drive method of the IRQ pin. 11 = Open Drain (asserted = 0, deasserted = Hi-Z) 10 = Open Source (asserted = 1, deasserted = Hi-Z) 01 = CMOS (asserted = 1, deasserted = 0) 00 = CMOS Inverted (asserted = 0, deasserted = 1)
3
2 1:0
Table 9. SERDES Control
Addr: 0x06 7 6 Reserved 5 REG_SERDES_CTL 4 3 SERDES Enable 2 1 EOF Length Default: 0x03 0
Bit 7:4 3
Name Reserved SERDES Enable
Description These bits are reserved and should be written with zeros. The SERDES Enable bit is used to switch between bit-serial mode and SERDES mode. 1 = SERDES enabled 0 = SERDES disabled, bit-serial mode enabled When the SERDES is enabled data can be written to and read from the IC one byte at a time through the use of the SERDES Data registers. The bit-serial mode requires bits to be written one bit at a time through the use of the DIO/DIOVAL pins. It is recommended that the SERDES mode be used to avoid the need to manage the timing required by the bit-serial mode. The End of Frame Length bits are used to set the number of sequential bit times for an inter-frame gap without valid data before an EOF event is generated. When in receive mode and a valid bit has been received the EOF event can then be identified by the number of bit times that expire without correlating any new data. The EOF event causes data to be moved to the proper SERDES Data Register and can also be used to generate interrupts. If 0 is the EOF length, an EOF condition will occur at the first invalid bit after a valid reception.
2:0
EOF Length
Table 10. Receive Interrupt Enable
Addr: 0x07 7 Underflow B 6 Overflow B 5 EOF B REG_RX_INT_EN 4 Full B 3 Underflow A 2 Overflow A 1 EOF A Default: 0x00 0 Full A
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Bit 7
Name Underflow B
Description The Underflow B bit is used to enable the interrupt associated with an underflow condition with the Receive SERDES Data B register (Reg 0x0B) 1 = Underflow B interrupt enabled for Receive SERDES Data B 0 = Underflow B interrupt disabled for Receive SERDES Data B An underflow condition occurs when attempting to read the Receive SERDES Data B register (Reg 0x0B) when it is empty. The Overflow B bit is used to enable the interrupt associated with an overflow condition with the Receive SERDES Data B register (Reg 0x0B) 1 = Overflow B interrupt enabled for Receive SERDES Data B 0 = Overflow B interrupt disabled for Receive SERDES Data B An overflow condition occurs when new received data is written into the Receive SERDES Data B register (Reg 0x0B) before the prior data is read out. The End of Frame B bit is used to enable the interrupt associated with the Channel B Receiver EOF condition. 1 = EOF B interrupt enabled for Channel B Receiver 0 = EOF B interrupt disabled for Channel B Receiver The EOF IRQ asserts during an End of Frame condition. End of Frame conditions occur after at least one bit has been detected, and then the number of invalid bits in the frame exceeds the number in the EOF length field. If 0 is the EOF length, and EOF condition will occur at the first invalid bit after a valid reception. This IRQ is cleared by reading the receive status register The Full B bit is used to enable the interrupt associated with the Receive SERDES Data B register (Reg 0x0B) having data placed in it. 1 = Full B interrupt enabled for Receive SERDES Data B 0 = Full B interrupt disabled for Receive SERDES Data B A Full B condition occurs when data is transferred from the Channel B Receiver into the Receive SERDES Data B register (Reg 0x0B). This could occur when a complete byte is received or when an EOF event occurs whether or not a complete byte has been received. The Underflow A bit is used to enable the interrupt associated with an underflow condition with the Receive SERDES Data A register (Reg 0x09) 1 = Underflow A interrupt enabled for Receive SERDES Data A 0 = Underflow A interrupt disabled for Receive SERDES Data A An underflow condition occurs when attempting to read the Receive SERDES Data A register (Reg 0x09) when it is empty. The Overflow A bit is used to enable the interrupt associated with an overflow condition with the Receive SERDES Data A register (0x09) 1 = Overflow A interrupt enabled for Receive SERDES Data A 0 = Overflow A interrupt disabled for Receive SERDES Data A An overflow condition occurs when new receive data is written into the Receive SERDES Data A register (Reg 0x09) before the prior data is read out. The End of Frame A bit is used to enable the interrupt associated with an End of Frame condition with the Channel A Receiver. 1 = EOF A interrupt enabled for Channel A Receiver 0 = EOF A interrupt disabled for Channel A Receiver The EOF IRQ asserts during an End of Frame condition. End of Frame conditions occur after at least one bit has been detected, and then the number of invalid bits in a frame exceeds the number in the EOF length field. If 0 is the EOF length, an EOF condition will occur at the first invalid bit after a valid reception. This IRQ is cleared by reading the receive status register. The Full A bit is used to enable the interrupt associated with the Receive SERDES Data A register (0x09) having data written into it. 1 = Full A interrupt enabled for Receive SERDES Data A 0 = Full A interrupt disabled for Receive SERDES Data A A Full A condition occurs when data is transferred from the Channel A Receiver into the Receive SERDES Data A register (Reg 0x09). This could occur when a complete byte is received or when an EOF event occurs whether or not a complete byte has been received.
6
Overflow B
5
EOF B
4
Full B
3
Underflow A
2
Overflow A
1
EOF A
0
Full A
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Table 11. Receive Interrupt Status
Addr: 0x08 7 Valid B Note: 6 Flow Violation B 5 EOF B REG_RX_INT_STAT 4 Full B 3 Valid A 2 Flow Violation A 1 EOF A Default: 0x00 0 Full A
All status bits are set and readable in the registers regardless of IRQ enable status. This allows a polling scheme to be implemented without enabling IRQs. The status bits are affected by the TX Enable and RX Enable (Reg 0x03, bits 7:6). For example, the receive status will read 0 if the IC is not in receive mode. These register are read-only.
Bit 7
Name Valid B
Description The Valid B bit is true when all the bits in the Receive SERDES Data B register (Reg 0x0B) are valid. 1 = All bits are valid for Receive SERDES Data B 0 = Not all bits are valid for Receive SERDES Data B When data is written into the Receive SERDES Data B register (Reg 0x0B) this bit is set if all of the bits within the byte that has been written are valid. This bit cannot generate an interrupt.
6
Flow Violation B The Flow Violation B bit is used to signal whether an overflow or underflow condition has occurred for the Receive SERDES Data B register (Reg 0x0B). 1 = Overflow/underflow interrupt pending for Receive SERDES Data B 0 = No overflow/underflow interrupt pending for Receive SERDES Data B Overflow conditions occur when the radio loads new data into the Receive SERDES Data B register (Reg 0x0B) before the prior data has been read. Underflow conditions occur when trying to read the Receive SERDES Data B register (Reg 0x0B) when the register is empty. This bit is cleared by reading the Receive Interrupt Status register (Reg 0x08) EOF B The End of Frame B bit is used to signal whether an EOF event has occurred on the Channel B receive. 1 = EOF interrupt pending for Channel B 0 = No EOF interrupt pending for Channel B An EOF condition occurs for the Channel B Receiver when receive has begun and then the number of bit times specified in the SERDES Control register (Reg 0x06) elapse without any valid bits being received. This bit is cleared by reading the Receive Interrupt Status register (Reg 0x08) The Full B bit is used to signal when the Receive SERDES Data B register (Reg 0x0B) is filled with data. 1 = Receive SERDES Data B full interrupt pending 0 = No Receive SERDES Data B full interrupt pending A Full B condition occurs when data is transferred from the Channel B Receiver into the Receive SERDES Data B register (Reg 0x0B). This could occur when a complete byte is received or when an EOF event occurs whether or not a complete byte has been received. The Valid A bit is true when all of the bits in the Receive SERDES Data A Register (Reg 0x09) are valid. 1 = All bits are valid for Receive SERDES Data A 0 = Not all bits are valid for Receive SERDES Data A When data is written into the Receive SERDES Data A register (Reg 0x09) this bit is set if all of the bits within the byte that has been written are valid. This bit cannot generate an interrupt.
5
4
Full B
3
Valid A
2
Flow Violation A The Flow Violation A bit is used to signal whether an overflow or underflow condition has occurred for the Receive SERDES Data A register (Reg 0x09). 1 = Overflow/underflow interrupt pending for Receive SERDES Data A 0 = No overflow/underflow interrupt pending for Receive SERDES Data A Overflow conditions occur when the radio loads new data into the Receive SERDES Data A register (Reg 0x09) before the prior data has been read. Underflow conditions occur when trying to read the Receive SERDES Data A register (Reg 0x09) when the register is empty. This bit is cleared by reading the Receive Interrupt Status register (Reg 0x08)
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1 EOF A The End of Frame A bit is used to signal whether an EOF event has occurred on the Channel A receive. 1 = EOF interrupt pending for Channel A 0 = No EOF interrupt pending for Channel A An EOF condition occurs for the Channel A Receiver when receive has begun and then the number of bit times specified in the SERDES Control register (0x06) elapse without any valid bits being received. This bit is cleared by reading the Receive Interrupt Status register (Reg 0x08). The Full A bit is used to signal when the Receive SERDES Data A register (Reg 0x09) is filled with data. 1 = Receive SERDES Data A full interrupt pending 0 = No Receive SERDES Data A full interrupt pending A Full A condition occurs when data is transferred from the Channel A Receiver into the Receive SERDES Data A Register (Reg 0x09). This could occur when a complete byte is received or when an EOF event occurs whether or not a complete byte has been received.
0
Full A
Table 12. Receive SERDES Data A
Addr: 0x09 7 6 5 REG_RX_DATA_A 4 Data 3 2 1 Default: 0x00 0
Bit 7:0
Name Data
Description Received Data for Channel A. The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only.
Table 13. Receive SERDES Valid A
Addr: 0x0A 7 6 5 REG_RX_VALID_A 4 Valid 3 2 1 Default: 0x00 0
Bit 7:0
Name Valid
Description These bits indicate which of the bits in the Receive SERDES Data A register (Reg 0x09) are valid. A "1" indicates that the corresponding data bit is valid for Channel A. If the Valid Data bit is set in the Receive Interrupt Status register (Reg 0x08) all eight bits in the Receive SERDES Data A register (Reg 0x09) are valid. Therefore, it is not necessary to read the Receive SERDES Valid A register (Reg 0x0A). The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only.
Table 14. Receive SERDES Data B
Addr: 0x0B 7 6 5 REG_RX_DATA_B 4 Data 3 2 1 Default: 0x00 0
Bit 7:0
Name Data
Description Received Data for Channel B. The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only.
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Table 15. Receive SERDES Valid B
Addr: 0x0C 7 6 5 REG_RX_VALID_B 4 Valid 3 2 1 Default: 0x00 0
Bit 7:0
Name Valid
Description These bits indicate which of the bits in the Receive SERDES Data B register (Reg 0x0B) are valid. A "1" indicates that the corresponding data bit is valid for Channel B. If the Valid Data bit is set in the Receive Interrupt Status register (0x08) all eight bits in the Receive SERDES Data B register (Reg 0x0B) are valid. Therefore, it is not necessary to read the Receive SERDES Valid B register (Reg 0x0C).The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only.
Table 16. Transmit Interrupt Enable
Addr: 0x0D 7 6 Reserved 5 REG_TX_INT_EN 4 3 Underflow 2 Overflow 1 Done Default: 0x00 0 Empty
Bit 7:4 3
Name Reserved Underflow
Description These bits are reserved and should be written with zeros. The Underflow bit is used to enable the interrupt associated with an underflow condition associated with the Transmit SERDES Data register (Reg 0x0F) 1 = Underflow interrupt enabled 0 = Underflow interrupt disabled An underflow condition occurs when attempting to transmit while the Transmit SERDES Data register (Reg 0x0F) does not have any data. The Overflow bit is used to enabled the interrupt associated with an overflow condition with the Transmit SERDES Data register (0x0F). 1 = Overflow interrupt enabled 0 = Overflow interrupt disabled An overflow condition occurs when attempting to write new data to the Transmit SERDES Data register (Reg 0x0F) before the preceding data has been transferred to the transmit shift register. The Done bit is used to enable the interrupt that signals the end of the transmission of data. 1 = Done interrupt enabled 0 = Done interrupt disabled The Done condition occurs when the Transmit SERDES Data register (Reg 0x0F) has transmitted all of its data and there is no more data for it to transmit. The Empty bit is used to enable the interrupt that signals when the Transmit SERDES register (Reg 0x0F) is empty. 1 = Empty interrupt enabled 0 = Empty interrupt disabled The Empty condition occurs when the Transmit SERDES Data register (Reg 0x0F) is loaded into the transmit buffer and it's safe to load the next byte
2
Overflow
1
Done
0
Empty
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Table 17. Transmit Interrupt Status
Addr: 0x0E 7 Note: 6 Reserved 5 REG_TX_INT_STAT 4 3 Underflow 2 Overflow 1 Done Default: 0x00 0 Empty
All status bits are set and readable in the registers regardless of IRQ enable status. This allows a polling scheme to be implemented without enabling IRQs. The status bits are affected by the TX Enable and RX Enable (Reg 0x03, bits 7:6). For example, the transmit status will read 0 if the IC is not in transmit mode. These registers are read-only.
Bit 7:4 3
Name Reserved Underflow
Description These bits are reserved. This register is read-only. The Underflow bit is used to signal when an underflow condition associated with the Transmit SERDES Data register (Reg 0x0F) has occurred. 1 = Underflow Interrupt pending 0 = No Underflow Interrupt pending This IRQ will assert during an underflow condition to the Transmit SERDES Data register (Reg 0x0F). An underflow occurs when the transmitter is ready to sample transmit data, but there is no data ready in the Transmit SERDES Data register (Reg 0x0F). This will only assert after the transmitter has transmitted at least one bit. This bit is cleared by reading the Transmit Interrupt Status register (Reg 0x0E). The Overflow bit is used to signal when an overflow condition associated with the Transmit SERDES Data register (0x0F) has occurred. 1 = Overflow Interrupt pending 0 = No Overflow Interrupt pending This IRQ will assert during an overflow condition to the Transmit SERDES Data register (Reg 0x0F). An overflow occurs when the new data is loaded into the Transmit SERDES Data register (Reg 0x0F) before the previous data has been sent. This bit is cleared by reading the Transmit Interrupt Status register (Reg 0x0E). The Done bit is used to signal the end of a data transmission. 1 = Done Interrupt pending 0 = No Done Interrupt pending This IRQ will assert when the data is finished sending a byte of data and there is no more data to be sent. This will only assert after the transmitter has transmitted as least one bit. This bit is cleared by reading the Transmit Interrupt Status register (Reg 0x0E) The Empty bit is used to signal when the Transmit SERDES Data register (Reg 0x0F) has been emptied. 1 = Empty Interrupt pending 0 = No Empty Interrupt pending This IRQ will assert when the transmit SERDES is empty. When this IRQ is asserted it is ok to write to the Transmit SERDES Data register (Reg 0x0F). Writing the Transmit SERDES Data register (Reg 0x0F) will clear this IRQ. It will be set when the data is loaded into the transmitter, and it is ok to write new data.
2
Overflow
1
Done
0
Empty
Note:
1. All status bits are set and readable in the registers regardless of IRQ enable status. This allows a polling scheme to be implemented without enabling IRQs. The status bits are affected by the TX Enable and RX Enable (Reg 0x03, bits 7:6). For example, the transmit status will read 0 if the IC is not in transmit mode. These registers are read-only.
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Table 18. Transmit SERDES Data
Addr: 0x0F 7 6 5 REG_TX_DATA 4 Data 3 2 1 Default: 0x00 0
Bit 7:0
Name Data
Description Transmit Data. The over-the-air transmitted order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7.
Table 19. Transmit SERDES Valid
Addr: 0x10 7 6 5 REG_TX_VALID 4 Valid 3 2 1 Default: 0x00 0
Bit 7:0
Name Valid
(1)
Description The Valid bits are used to determine which of the bits in the Transmit SERDES Data register (reg 0x0F) are valid. 1 = Valid transmit bit 0 = Invalid transmit bit
Note:
1. The Valid bit in the Transmit SERDES Valid register (Reg 0x10) is used to mark whether the radio will send data or preamble during that bit time of the data byte. Data is sent LSB first. The SERDES will continue to send data until there are no more VALID bits in the shifter. For example, writing 0x0F to the Transmit SERDES Valid register (Reg 0x10) will send half a byte.
Table 20. PN Code
Addr: 0x11-18 REG_PN_CODE Default: 0x1E8B6A3DE0E9B222 Address 0x15
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Address 0x18 Address 0x17 Address 0x16
31
30
29 28 27 26 Address 0x14
25
24 23
22
21 20 19 18 Address 0x13
17
16
15
14
13 12 11 10 Address 0x12
9
8
7
6
5 4 3 2 Address 0x11
1
0
Bit 63:0
Name PN Codes
Description The value inside the 8 byte PN code register is used as the spreading code for DSSS communication. All 8 bytes can be used together for 64 chips/bit PN code communication, or the registers can be split into two sets of 32 chips/bit PN codes and these can be used alone or with each other to accomplish faster data rates. Not any 64 chips/bit value can be used as a PN code as there are certain characteristics that are needed to minimize the possibility of multiple PN codes interfering with each other or the possibility of invalid correlation. The over-the-air order is bit 0 followed by bit 1, followed by bit 62, followed by bit 63.
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Table 21. Threshold Low
Addr: 0x19 7 Reserved 6 5 REG_THRESHOLD_L 4 3 Threshold Low 2 1 Default: 0x08 0
Bit 7 6:0
Name Reserved Threshold Low
Description This bit is reserved and should be written with zero. The Threshold Low value is used to determine the number of missed chips allowed when attempting to correlate a single data bit of value 0. A perfect reception of a data bit of 0 with a 64 chips/bit PN code would result in zero correlation matches, meaning the exact inverse of the PN code has been received. By setting the Threshold Low value to 0x08 for example, up to eight chips can be erroneous while still identifying the value of the received data bit. This value along with the Threshold High value determine the correlator count values for logic 1 and logic 0. The threshold values used determine the sensitivity of the receiver to interference and the dependability of the received data. By allowing a minimal number of erroneous chips the dependability of the received data increases while the robustness to interference decreases. On the other hand increasing the maximum number of missed chips means reduced data integrity but increased robustness to interference and increased range.
Table 22. Threshold High
Addr: 0x1A 7 Reserved 6 5 REG_THRESHOLD_H 4 3 Threshold High 2 1 Default: 0x38 0
Bit 7 6:0
Name Reserved Threshold High
Description This bit is reserved and should be written with zero. The Threshold High value is used to determine the number of matched chips allowed when attempting to correlate a single data bit of value 1. A perfect reception of a data bit of 1 with a 64 chips/bit or a 32 chips/bit PN code would result in 64 chips/bit or 32 chips/bit correlation matches, respectively, meaning every bit was received perfectly. By setting the Threshold High value to 0x38 (64-8) for example, up to eight chips can be erroneous while still identifying the value of the received data bit. This value along with the Threshold Low value determine the correlator count values for logic 1 and logic 0. The threshold values used determine the sensitivity of the receiver to interference and the dependability of the received data. By allowing a minimal number of erroneous chips the dependability of the received data increases while the robustness to interference decreases. On the other hand increasing the maximum number of missed chips means reduced data integrity but increased robustness to interference and increased range.
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Table 23. Wake Enable
Addr: 0x1C 7 6 5 REG_WAKE_EN 4 Reserved 3 2 1 Default: 0x00 0 Wake-up Enable
Bit 7:1 0
Name Reserved Wake-up Enable
Description These bits are reserved and should be written with zeros. Wake-up interrupt enable. 0 = Disabled 1 = Enabled A wake-up event is triggered when the PD pin is deasserted and once the IC is ready to receive SPI communications.
Table 24. Wake Status
Addr: 0x1D 7 6 5 REG_WAKE_STAT 4 Reserved 3 2 1 Default: 0x01 0 Wake-up Status
Bit 7:1 0
Name Reserved Wake-up Status
Description These bits are reserved. This register is read-only. Wake-up status. 0 = Wake interrupt not pending 1 = Wake interrupt pending This IRQ will assert when a wake-up condition occurs. This bit is cleared by reading the Wake Status register (Reg 0x1D). This register is read-only.
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Table 25. Analog Control
Addr: 0x20 7 Reserved 6 AGC Disable 5 MID Read Enable REG_ANALOG_CTL 4 Reserved 3 Reserved 2 PA Output Enable 1 PaInv Default: 0x00 0 Rst
Bit 7 6 5
Name Reserved AGC RSSI Control MID Read Enable Reserved PA Output Enable
Description This bit is reserved and should be written with zero. Enables AGC/RSSI control via Reg 0x2E and Reg 0x2F. The MID Read Enable bit must be set to read the contents of the Manufacturing ID register (Reg 0x3C-0x3F). Enabling the Manufacturing ID register (Reg 0x3C-0x3F) consumes power. This bit should only be set when reading the contents of the Manufacturing ID register (Reg 0x3C-0x3F). These bits are reserved and should be written with zeros. The Power Amplifier Output Enable bit is used to enable the PACTL pin for control of an external power amplifier. 1 = PA Control Output Enabled on PACTL pin 0 = PA Control Output Disabled on PACTL pin The Power Amplifier Invert bit is used to specify the polarity of the PACTL signal when the PaOe bit is set high. PA Output Enable and PA Invert cannot be simultaneously changed. 1 = PACTL active low 0 = PACTL active high The Reset bit is used to generate a self clearing device reset. 1 = Device Reset. All registers are restored to their default values 0 = No Device Reset
4:3 2
1
PA Invert
0
Reset
Table 26. Channel
Addr: 0x21 7 A+N 6 5 REG_CHANNEL 4 3 Channel 2 1 Default: 0x00 0
Bit 7
Name A+N
Description The A+N bit is used to specify whether the Synthesizer frequency is generated through the use of the Channel register (Reg 0x21) or through the use of the Synthesizer A Counter register (Reg 0x01) and the Synthesizer N Counter register (Reg 0x02). 1 = Synthesizer A Counter register (Reg 0x01) and the Synthesizer N Counter register (Reg 0x02) registers used to generate Synthesizer frequency 0 = Channel register (Reg 0x21) is used to generate Synthesizer frequency When set to 1 the channel value is ignored and the values written in the Synthesizer A Counter register (Reg 0x01) and the Synthesizer N Counter register (Reg 0x02) are used. When set to 0 the values written to the Synthesizer A Counter register (Reg 0x01) and the Synthesizer N Counter register (Reg 0x02) are ignored and the channel value is used by the synthesizer. It is recommended that the Channel register (Reg 0x21) is used as opposed to the Synthesizer A Counter register (Reg 0x01) and the Synthesizer N Counter register (Reg 0x02) method. The Channel register (Reg 0x21) is used to determine the Synthesizer frequency when the A+N bit is set to 0. Use of other channels may be restricted by certain regulatory agencies. A value of 1 corresponds to a communication frequency of 2.402 GHz, while a value of 79 corresponds to a frequency of 2.479 GHz. The channels are separated from each other by 1 MHz intervals.
6:0
Channel
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Table 27. Receive Signal Strength Indicator (RSSI)
Addr: 0x22 7 Reserved Note: 6 5 Valid 4 REG_RSSI 3 2 RSSI 1 Default: 0x00 0
The RSSI will collect a single value each time the part is put into receive mode via Control register (Reg 0x03, bit 7 = 1).
Bit 7:6 5
Name Reserved Valid
Description These bits are reserved. This register is read-only. The Valid bit indicates whether the RSSI value in bits [4:0] are valid. This register is read only. 1 = RSSI value is valid 0 = RSSI value is invalid The Receive Strength Signal Indicator (RSSI) value indicates the strength of the received signal. This is a read only value with the higher values indicating stronger received signals meaning more reliable transmissions.
4:0
RSSI
Table 28. Power Control
Addr: 0x23 7 6 5 Reserved 4 REG_PA 3 2 1 PA Bias Default: 0x00 0
Bit 7:3 2:0
Name Reserved PA Bias
Description These bits are reserved and should be written with zeros. The Power Amplifier Bias (PA Bias) bits are used to set the transmit power of the IC through increasing (values up to 7) or decreasing (values down to 0) the gain of the on-chip Power Amplifier. The higher the register value the higher the transmit power. By changing the PA Bias value signal strength management functions can be accomplished. For general purpose communication a value of 7 is recommended.
Table 29. Crystal Adjust
Addr: 0x24 7 Reserved 6 Clock Output Disable 5 REG_CRYSTAL_ADJ 4 3 Crystal Adjust 2 1 Default: 0x00 0
Bit 7 6
Name Reserved Clock Output Disable
Description This bit is reserved and should be written with zero. The Clock Output Disable bit disables the 13 MHz clock driven on the X13OUT pin. 1 = No 13 MHz clock driven externally 0 = 13 MHz clock driven externally If the 13 MHz clock is driven on the X13OUT pin then receive sensitivity will be reduced by -4 dBm on channels 5+13n. By default the 13 MHz clock output pin is enabled. This pin is useful for adjusting the 13 MHz clock, but it interferes with every 13th channel beginning with 2.405 GHz channel. Therefore, it is recommended that the 13 MHz clock output pin be disabled when not in use. The Crystal Adjust value is used to calibrate the on-chip load capacitance supplied to the crystal. The Crystal Adjust value will depend on the parameters of the crystal being used. Refer to the appropriate reference material for information about choosing the optimum Crystal Adjust value.
5:0
Crystal Adjust
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Table 30. VCO Calibration
Addr: 0x26 7 6 5 VCO Slope Enable REG_VCO_CAL 4 3 Reserved 2 1 Default: 0x00 0
Bit 7:6
Name VCO Slope Enable (Write-Only)
Description The Voltage Controlled Oscillator (VCO) Slope Enable bits are used to specify the amount of variance automatically added to the VCO. 11 = -5/+5 VCO adjust. The application MCU must configure this option during initialization 10 = -2/+3 VCO adjust 01 = Reserved 00 = No VCO adjust These bits are undefined for read operations. These bits are reserved and should be written with zeros.
5:0
Reserved
Table 31. AGC Control
Addr: 0x2E 7 AGC Lock 6 5 REG_AGC_CTL 4 3 Reserved 2 1 Default: 0x00 0
Bit 7
Name AGC Lock
Description When set, this bit disables the on-chip LNA AGC system, powers down unused circuitry, and locks the LNA to maximum gain. The user must set Reg 20, bit 6 = 1 to enable writes to Reg 0x2E. It is recommended this bit be set during initialization to save power. These bits are reserved and should be written with zeros.
6:0
Reserved
Table 32. Carrier Detect
Addr: 0x2F 7 Carrier Detect Override 6 5 REG_CARRIER_DETECT 4 3 Reserved 2 1 Default: 0x00 0
Bit 7 6:0
Name Carrier Detect Override Reserved
Description When set, this bit overrides the carrier detect. The user must set Reg 20, bit 6 = 1 to enable writes to Reg 0x2F. These bits are reserved and should be written with zeros.
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Table 33. Clock Manual
Addr: 0x32 7 6 5 REG_CLOCK_MANUAL 4 3 2 1 Manual Clock Overrides Default: 0x00 0
Bit 7:0
Name Manual Clock Overrides
Description This register must be written with 0x41 after reset for correct operation
Table 34. Clock Enable
Addr: 0x33 7 6 5 REG_CLOCK_ENABLE 4 3 2 1 Manual Clock Enables Default: 0x00 0
Bit 7:0
Name Manual Clock Enables
Description This register must be written with 0x41 after reset for correct operation
Table 35. Synthesizer Lock Count
Addr: 0x38 7 6 5 REG_SYN_LOCK_CNT 4 Count 3 2 1 Default: 0x64 0
Bit 7:0
Name Count
Description Determines the length of delay in 2 s increments for the synthesizer to lock when auto synthesizer is enabled via Control register (0x03, bit 1 = 0) and not using the PLL lock signal.
Table 36. Manufacturing ID
Addr: 0x3C-3F REG_MID 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Address 0x3F Address 0x3E Address 0x3D
Address 0x3C
Bit 31:0
Name Address[31:0]
Description These bits are the Manufacturing ID (MID) for each IC. The contents of these bits cannot be read unless the MID Read Enable bit (bit 5) is set in the Analog Control register (Reg 0x20). Enabling the Manufacturing ID register (Reg 0x3C-0x3F) consumes power. The MID Read Enable bit in the Analog Control register (Reg 0x20, bit 5) should only be set when reading the contents of the Manufacturing ID register (Reg 0x3C to 0x3F). This register is read-only.
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Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Storage temperature Ambient temperature with power applied Supply voltage on VCC relative to VSS DC voltage to logic inputs
(1)
Pin
Symbol
Value -65 to +150 -55 to +125 -0.3 to +3.9 -0.3 to VCC +0.3 -0.3 to VCC +0.3 > 2000 500 +200, -200
Unit C C V V V V V mA
DC voltage applied to outputs in high-Z state Static discharge voltage (digital) Static discharge voltage (RF) Latch-up current Notes:
(2)
1. It is permissible to connect voltages above VCC to inputs through a series resistor limiting input current to 1 mA. This cannot be done during power down mode. AC timing not guaranteed. 2. Human Body Model (HBM).
Operating Conditions
Parameters Supply voltage Ambient temperature under bias Ground voltage Oscillator or crystal frequency) FOSC Symbol VCC TA Value 2.7 to 3.6 -40 to +85 0 13 Unit V C V MHz
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DC Parameters
Description Supply voltage Output high voltage condition 1 Output high voltage condition 2 Output low voltage Input high voltage Input low voltage Input leakage current Pin input capacitance (except X13, X13IN, RFIN) Current consumption during power-down mode Current consumption without synthesizer ICC from PD high to oscillator stable Average transmitter current consumption(3) Average transmitter current consumption(4) Current consumption during receive Current consumption during transmit Current consumption with synthesizer on, no transmit or receive Notes: No handshake With handshaking PD = LOW PD = HIGH 0 < VIN < VCC At IOH = -100.0 A At IOH = -2.0 mA At IOL = 2.0 mA Conditions Symbol VCC VOH1 VOH2 VOL VIH VIL IIL CIN ISleep IDLE ICC STARTUP ICC TX AVG ICC1 TX AVG ICC2 RX ICC
(PEAK)
Min. 2.7 VCC - 0.1 2.4 2.0 -0.3 -1
Typ.(1) 3.0 VCC 3.0 0.0
Max. 3.6
Unit V V V
0.4 VCC
(2)
V V V A pF A mA mA mA mA mA mA
+0.8 0.26 3.5 0.24 3 1.8 5.9 8.1 57.7 69.1 +1 10 10
TX ICC
(PEAK)
SYNTH SETTLE ICC
28.7
mA
1. Typical values measured with VCC = 3.0 V at 25C. 2. It is permissible to connect voltages above VCC to inputs through a series resistor limiting input current to 1 mA. 3. Average ICC when transmitting a 5-byte packet (3 data bytes + 2 bytes of protocol) every 10 ms using the WirelessUSB 1-way protocol. 4. Average ICC when transmitting a 5-byte packet (3 data bytes + 2 bytes of protocol) every 10 ms using the WirelessUSB 2-way protocol.
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ATR2434 [Preliminary]
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ATR2434 [Preliminary]
AC Characteristics(1): SPI Interface(3)
Description SPI clock period SPI clock high time SPI clock high time SPI clock low time SPI input data set-up time SPI input data hold time SPI output data valid time SPI slave select set-up time before first positive edge of SCK(4) SPI slave select hold time after last negative edge of SCK Notes: 1. 2. 3. 4. Parameter tSCK_CYC tSCK_HI (BURST READ)(2) tSCK_HI tSCK_LO tDAT_SU tDAT_HLD tDAT_VAL tSS_SU tSS_HLD Min. 476 238 158 158 10 97(3) 77(3) 250 80 174(3) Typ. Max. Unit ns ns ns ns ns ns ns ns ns
AC values are not guaranteed if voltages on any pin exceed VCC. This stretch only applies to every 9th SCK HI pulse for SPI burst reads only. For FOSC = 13 MHz, 3.3 V at 25C. SCK must start low, otherwise the success of SPI transactions are not guaranteed.
Figure 9. SPI Timing Diagram
tS CK _CY C tSCK_HI
SCK SS MOSI M IS O
tSCK _LO
D RI VE
tSS_SU tD AT_S U
SA
M
PL
E
tDA T_HLD
d a ta fro m m cu
tS S_HLD
d a ta fro m m c u d a ta fro m m cu d a ta
tDA T_VA L
d a ta to m c u d a ta to m c u d a ta
Figure 10. SPI Burst Read Every 9th SCK HI Stretch Timing Diagram
t SCK_CYC t S CK_HI
SCK SS M ISO
data to mcu every 8
th
t SCK _LO
D RI VE
t SCK _HI (BURS T RE AD)
every 9 th SCK _HI every 10th SC K_HI
SCK_HI
DR
IV
D E
RI
VE
data to mcu
data to mcu
data
t D AT_VA L
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DIO Interface
Parameter Transmit tTX_DIOVAL_SU tTX_DIO_SU tTX_DIOVAL_HLD tTX_DIO_HLD tTX_IRQ_HI DIOVAL set-up time DIO set-up time DIOVAL hold time DIO hold time Minimum IRQ high time - 32 chips/bit DDR Minimum IRQ high time - 32 chips/bit Minimum IRQ high time - 64 chips/bit Minimum IRQ low time - 32 chips/bit DDR tTX_IRQ_LO Receive DIOVAL valid time - 32 chips/bit DDR tRX_DIOVAL_VLD DIOVAL valid time - 32 chips/bit DIOVAL valid time - 64 chips/bit DIO valid time - 32 chips/bit DDR tRX_DIO_VLD DIO valid time - 32 chips/bit DIO valid time - 64 chips/bit Minimum IRQ high time - 32 chips/bit DDR tRX_IRQ_HI Minimum IRQ high time - 32 chips/bit Minimum IRQ high time - 64 chips/bit Minimum IRQ low time - 32 chips/bit DDR tRX_IRQ_LO Minimum IRQ low time - 32 chips/bit Minimum IRQ low time - 64 chips/bit -0.01 -0.01 -0.01 -0.01 -0.01 -0.01 1 1 1 8 16 32 +6.1 +8.2 +16.1 +6.1 +8.2 +16.1 s s s s s s s s s s s s Minimum IRQ low time - 32 chips/bit Minimum IRQ low time - 64 chips/bit 2.1 2.1 0 0 8 16 32 8 16 32 s s s s s s s s s s Description Min. Typ. Max. Unit
Figure 11. DIO Receive Timing Diagram
tRX_IRQ_HI tRX_IRQ_LO
IRQ DIO/ DIOVAl
SA
MP LE
SA
MP LE
data
data
data
tRX_DIO_VLD tRX_DIOVAL_VLD
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ATR2434 [Preliminary]
4822C-ISM-09/04
ATR2434 [Preliminary]
Figure 12. DIO Transmit Timing Diagram
tTX_IRQ_HI tTX_IRQ_LO
IRQ DIO/ DIOVAl tTX_DIO_SU tTX_DIOVAL_SU
SA MP LE
SA MP LE
data
data
tTX_DIO_HLD tTX_DIOVAL_HLD
Radio Parameters
Parameter Description RF frequency range Sensitivity Maximum received signal RSSI value for PWRin > -40 dBm RSSI value for PWRin < -95 dBm Interference Performance Co-channel interference rejection Carrier-to-Interference (C/I) Adjacent (1 MHz) channel selectivity C/I 1 MHz Adjacent (2 MHz) channel selectivity C/I 2 MHz Adjacent (> 3 MHz) channel selectivity C/I > 3 MHz Image
(2)
Conditions
(1)
Min. 2.400 -85 -20
Typ.
Max. 2.483
Unit GHz dBm dBm
Radio Receiver (VCC = 3.3 V, fosc = 13.000 MHz, X13OUT off, 64 chips/bit, Threshold Low = 8, Threshold High = 56, BER < 10-3) -95 -6 28 31 0 -10 C = -60 dBm C = -60 dBm C = -60 dBm C = -67 dBm C = -67 dBm C = -67 dBm 9 -2 -32 -40 -31 -38 dB dB dB dB dB dB
frequency interference, C/I image
Adjacent (1 MHz) interference to in-band image frequency, C/I image 1 MHz Out-of-band Blocking Interference Signal Frequency 30 MHz to 2399 MHz except (FO/N and FO/N 1 MHz)(3) 2498 MHz to 12.75 GHz, except (FO/N and FO x N 1 MHz) Intermodulation Spurious Emission 30 MHz to 1 GHz 1 GHz to 12.75 GHz except (4.8 GHz to 5.0 GHz) 4.8 GHz to 5.0 GHz Radio Transmitter (VCC = 3.3 V, fosc = 13.000 MHz) Maximum RF transmit power RF power control range Notes: 1. 2. 3. 4.
(3)
C = -67 dBm C = -67 dBm C = -64 dBm f = 5,10 MHz
-24 -22 -31
dBm dBm dBm
-57 -47 -37(4) PA = 7 -0.5 28.9
dBm dBm dBm dBm dB
Subject to regulation. Image frequency is +4 MHz from desired channel (2 MHz low IF, high side injection). FO = Tuned Frequency, N = Integer. Antenna matching network and antenna will attenuate the output signal at these frequencies to meet regulatory requirements.
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4822C-ISM-09/04
Radio Parameters (Continued)
Parameter Description RF power range control step size Frequency deviation Frequency deviation Zero crossing eError Occupied bandwidth Initial frequency offset In-band Spurious Second channel power (2 MHz) Third channel power (>3 MHz) Non-Harmonically Related Spurs 30 MHz to 12.75 GHz Harmonic Spurs Second harmonic Third harmonic Fourth and greater harmonics Notes: 1. 2. 3. 4. -20 -30 -47 dBm dBm dBm -57 dBm -41 -49 -30 -40 dBm dBm 100-kHz resolution bandwidth, -6 dBc 500 Conditions Seven steps, monotonic PN code pattern 10101010 PN code pattern 11110000 Min. Typ. 4.1 276 317 80 898 44.6 Max. Unit dB kHz kHz ns kHz kHz
Subject to regulation. Image frequency is +4 MHz from desired channel (2 MHz low IF, high side injection). FO = Tuned Frequency, N = Integer. Antenna matching network and antenna will attenuate the output signal at these frequencies to meet regulatory requirements.
Power Management Timing
Parameter tPDN_X13 tSPI_RDY tPWR_RST tRST tPWR_PD tWAKE tPD tSLEEP tWAKE_INT tSTABLE Notes: Description Time from PD deassert to X13OUT Time from oscillator stable to start of SPI transactions Power On to RESET deasserted Minimum RESET asserted pulse width Power on to PD deasserted(1) PD deassert to clocks running
(2)
Conditions
Min.
Typ 2000
Max.
Unit s s s s s
1 VCC at 2.7 V 1300 1 1300 2000 10 50 2000 to within 10 ppm 2100
s s s s s
Minimum PD asserted pulse width PD assert to low power mode PD deassert to IRQ(3) assert (wake interrupt)(4) PD deassert to clock stable
1. The PD pin must be asserted at power up to ensure proper crystal start-up. 2. When X13OUT is enabled. 3. Both the polarity and the drive method of the IRQ pin are programmable. See page 14 for more details. Figure 14 illustrates default values for the Configuration register (Reg 0x05, bits 1:0). 4. A wake-up event is triggered when the PD pin is deasserted. Figure 14 illustrates a wake-up event configured to trigger an IRQ pin event via the Wake Enable register (Reg 0x1C, bit 0 = 1).
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ATR2434 [Preliminary]
Figure 13. Power On Reset/Reset Timing
X 13O U T VCC RESET PD
tPDN_X13
S A T T R P U
t S P I_ R D Y
tPW R_RST tPW R_PD
tRST
Figure 14. Sleep/Wake Timing
X 13O U T
P E LE S
tW A KE
W
PD
tPD
E K A
t S LE E P
IR Q
tSTABLE
t W A K E _IN T
AC Test Loads and Waveforms for Digital Pins
Figure 15. AC Test Loads and Waveforms for Digital Pins
Q IR
AC Test Loads
OUTPUT 30 pF INCLUDING JIG AND SCOPE OUTPUT 5 pF INCLUDING JIG AND SCOPE
DC Test Load
VCC OUTPUT R2 R1
Max
Typical
ALL INPUT PULSES VCC GND Rise time: 1 V/ns Equivalent to: THEVENIN EQUIVALENT RTH VTH OUTPUT
Parameter R1 R2 RTH VTH VCC
1071 937 500 1.4 3.00
Unit V V
90% 10%
90% 10% Fall time: 1 V/ns
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4822C-ISM-09/04
Ordering Information
Extended Type Number ATR2434-PLT ATR2434-PLT Package QFN48 - 7x7 QFN48 - 7x7 Remarks Tray Samples
Package Information
34
ATR2434 [Preliminary]
4822C-ISM-09/04
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4822C-ISM-09/04

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